Finish rev2 of the PCB design.

[atreides.git] / atreus.rkt

diff --git a/atreus.rkt b/atreus.rkt
index b5abced33f1e709481554ac484145b0b1b8dd1f3..2195de9e4f707eea146bb5b20c6232d7afd9a042 100644 (file)
--- a/atreus.rkt
+++ b/atreus.rkt
@@ -122,7 +122,9 @@
     (pad D6 thru_hole circle (at -3.81 -6.35 270) (size 1.7526 1.7526)
          (drill 1.0922) (layers *.Cu *.SilkS *.Mask) (net 14 N-col-9))
     (pad RST thru_hole circle (at -1.27 -6.35 270) (size 1.7526 1.7526)
-       (drill 1.0922) (layers *.Cu *.SilkS *.Mask) (net 0 ""))))
+       (drill 1.0922) (layers *.Cu *.SilkS *.Mask) (net 0 ""))
+    (pad GND thru_hole circle (at 6.35 -6.35 270) (size 1.7526 1.7526)
+         (drill 1.0922) (layers *.Cu *.SilkS *.Mask) (net 0 ""))))
 
 (define nets
   `((net 0 "")
@@ -221,11 +223,11 @@
     (list (switch row col) (diode row col))))
 
 (define edge-cuts
-  (for/list [(s '([31 22] [84 22] [128 30] [128 54] [130 54] [130 60] [138 60]
-                  [138 54] [140 54] [140 30] [185 22]
+  (for/list [(s '([31 22] [84 22] [127 30] [127 54] [130 54] [130 60] [138 60]
+                  [138 54] [141 54] [141 30] [185 22]
                   [237 22] [250 95] [161 112] [107 112] [18 95]))
-             (e '([84 22] [128 30] [128 54] [130 54] [130 60] [138 60] [138 54]
-                  [140 54] [140 30] [185 22]
+             (e '([84 22] [127 30] [127 54] [130 54] [130 60] [138 60] [138 54]
+                  [141 54] [141 30] [185 22]
                   [237 22] [250 95] [161 112] [107 112] [18 95] [31 22]))]
     `(gr_line (start ,@s) (end ,@e) (angle 90) (layer Edge.Cuts) (width 0.3))))